Search - usb 1.1 ip core

[VHDL-FPGA-Verilog] USB 1.1 IP-CORE和设计范例 VHDL源代码

Description: USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
Platform: | Size: 425984 | Author: ken | Hits:

[VHDL-FPGA-Verilog] usb1.1_Verilog

Description: usb1.1的设备控制器IP核，是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.
Platform: | Size: 131072 | Author: 李恒 | Hits:

[VHDL-FPGA-Verilog] USB IPcore（带说明）

Description: USB IPcoreIP核，包含文档（带说明）-USB IPcoreIP nuclear contains documents (with the note)
Platform: | Size: 408576 | Author: 陈友荣 | Hits:

[VHDL-FPGA-Verilog] USB 2.0 IP Core

Description: USB20的IP CORE,可以直接用在SOPC下，自动完成全部的枚举，只需修改枚举参数即可！-USB20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
Platform: | Size: 181248 | Author: 林风 | Hits:

[Other] free_IP_1

Description: 来自于OpenCores组织的开放IP核，非常专业，大牛编写。-OpenCores organizations from open IP core, very professional, big cattle preparation.
Platform: | Size: 2644992 | Author: wangyunshann | Hits:

[USB develop] usb_phy

Description: usb接口协议。It was tested with a USB 1.1 core I have written on a XESS XCV800 board with a a Philips PDIUSBP11A transceiver. -usb interface protocol. It was tested with a USB 1.1 core I have written ona XESS XCV800 board with aa Philips PDIUSBP11A transceiver.
Platform: | Size: 11264 | Author: 颜新卉 | Hits:

[USB develop] usb20_ipcore_usb_funct

Description: usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL description suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
Platform: | Size: 208896 | Author: road | Hits:

[VHDL-FPGA-Verilog] USB

Description: 用VHDL实现的USB IP核，大家可以参考下-Use VHDL to achieve USB IP core, we can refer to the following
Platform: | Size: 1146880 | Author: 蔡飞 | Hits:

[USB develop] usb

Description: USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
Platform: | Size: 6144 | Author: polito | Hits:

[Other] slaveController

Description: 对USB的从机设备的IP核进行了重新设计并在一定程度上进行了优化-On the USB device from the IP core has been redesigned to some extent, is optimized
Platform: | Size: 56320 | Author: shaqiu | Hits:

[VHDL-FPGA-Verilog] 1

Description: 15个免费的IP核 usb11,i2c,pci_core,video_compression_systems等等.-15 free IP core usb11, i2c, pci_core, video_compression_systems and so on.
Platform: | Size: 2646016 | Author: likufan | Hits:

[source in ebook] USB_xilinx

Description: USB应用的IP核心，需要深入了解核心的行为。建立本诀窍是大大简化了全面参考应用。-Application of IP-Cores requires in-depth knowledge of the core’s behavior. Building up this know-how is greatly simplified by comprehensive reference applications.
Platform: | Size: 462848 | Author: 黎明 | Hits:

[VHDL-FPGA-Verilog] usb_latest.tar

Description: 用VHDL语言编写的USB 2.0IP核。USB 2.0的传输速率是高速率480 Mb/s，需要再外扩一个PHY。-This is a USB 2.0 compliant core，USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
Platform: | Size: 196608 | Author: liang | Hits:

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[VHDL-FPGA-Verilog] USB 1.1 IP-CORE和设计范例 VHDL源代码

[VHDL-FPGA-Verilog] usb1.1_Verilog

[VHDL-FPGA-Verilog] USB IPcore（带说明）

[VHDL-FPGA-Verilog] USB 2.0 IP Core

[Other] free_IP_1

[USB develop] usb_phy

[USB develop] usb20_ipcore_usb_funct

[VHDL-FPGA-Verilog] USB

[USB develop] usb

[Other] slaveController

[VHDL-FPGA-Verilog] 1

[source in ebook] USB_xilinx

[VHDL-FPGA-Verilog] usb_latest.tar

[VHDL-FPGA-Verilog] usb

[VHDL-FPGA-Verilog] verilog-usb--protel-design

[USB develop] USB-1.1-IP-CORE-VHDL

[VHDL-FPGA-Verilog] USB_Verilog_IP

[VHDL-FPGA-Verilog] USB2.0-IP

[USB develop] USB-IPcore-Verilog

[Documents] pg137-axi-usb2-device(xilinx USB ip core)

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